<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>Appuntiperscuola.it &#187; Sistemi digitali</title>
	<atom:link href="https://www.appuntiperscuola.it/elettronica/sistemi-digitali/feed/" rel="self" type="application/rss+xml" />
	<link>https://www.appuntiperscuola.it</link>
	<description>Il sito di appunti per tutti gli studenti</description>
	<lastBuildDate>Tue, 28 Jul 2015 11:37:12 +0000</lastBuildDate>
	<language>it-IT</language>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
	<generator>https://wordpress.org/?v=4.2.38</generator>
	<item>
		<title>Analisi degli stati possibili di un circuito sequenziale sincrono</title>
		<link>https://www.appuntiperscuola.it/elettronica/analisi-degli-stati-possibili-di-un-circuito-sequenziale-sincrono/</link>
		<comments>https://www.appuntiperscuola.it/elettronica/analisi-degli-stati-possibili-di-un-circuito-sequenziale-sincrono/#comments</comments>
		<pubDate>Thu, 03 Feb 2011 11:05:49 +0000</pubDate>
		<dc:creator><![CDATA[admin]]></dc:creator>
				<category><![CDATA[Elettronica]]></category>
		<category><![CDATA[Sistemi digitali]]></category>

		<guid isPermaLink="false">http://localhost:8084/wordpress/?p=1164</guid>
		<description><![CDATA[1) Schematic 2) Timing diagram showing all the network states The clear is so short because, if it were low, all the quits would be low.   3) How many different configurations are actually possible? What are the possible state-codes (Q2,Q1,Q0)?   0 0 0;  1 0 0;1 1 1 ;0 1 1.  4) Which are [&#8230;]]]></description>
		<wfw:commentRss>https://www.appuntiperscuola.it/elettronica/analisi-degli-stati-possibili-di-un-circuito-sequenziale-sincrono/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Analisi di un contatore asincrono up-down</title>
		<link>https://www.appuntiperscuola.it/elettronica/analisi-di-un-contatore-asincrono-up-down/</link>
		<comments>https://www.appuntiperscuola.it/elettronica/analisi-di-un-contatore-asincrono-up-down/#comments</comments>
		<pubDate>Thu, 03 Feb 2011 09:49:28 +0000</pubDate>
		<dc:creator><![CDATA[admin]]></dc:creator>
				<category><![CDATA[Elettronica]]></category>
		<category><![CDATA[Sistemi digitali]]></category>

		<guid isPermaLink="false">http://localhost:8084/wordpress/?p=1159</guid>
		<description><![CDATA[1) Schematic   2) Timing diagram    3) The circuit is.     an asynchronous up and down counter. It is a circuit that do not have inputs (but    only the reset one), and that works in the same sequence in a close continue cycle.  4) Truth table of the combinational network: Q2 Q1 Q0 C2 [&#8230;]]]></description>
		<wfw:commentRss>https://www.appuntiperscuola.it/elettronica/analisi-di-un-contatore-asincrono-up-down/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Analisi di un 3-bit Shift-Register</title>
		<link>https://www.appuntiperscuola.it/elettronica/analisi-di-un-3-bit-shift-register/</link>
		<comments>https://www.appuntiperscuola.it/elettronica/analisi-di-un-3-bit-shift-register/#comments</comments>
		<pubDate>Thu, 03 Feb 2011 09:46:31 +0000</pubDate>
		<dc:creator><![CDATA[admin]]></dc:creator>
				<category><![CDATA[Elettronica]]></category>
		<category><![CDATA[Sistemi digitali]]></category>

		<guid isPermaLink="false">http://localhost:8084/wordpress/?p=1157</guid>
		<description><![CDATA[1) Schematic 2) Timing diagram 3) Sequence 0 &#8230; -4 &#8230; -2 &#8230; +3 &#8230; +1 &#8230; 0 Sequence Table: !Reset Data Clock Qa Qb Qc Dec 0 0 &#8211; 0 0 0 0 1 0 ↑ 0 0 0 0 1 1 ↑ 1 0 0 -4 1 1 ↑ 1 1 0 -2 [&#8230;]]]></description>
		<wfw:commentRss>https://www.appuntiperscuola.it/elettronica/analisi-di-un-3-bit-shift-register/feed/</wfw:commentRss>
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		</item>
		<item>
		<title>Analisi temporale di un D-Pet Flip Flop</title>
		<link>https://www.appuntiperscuola.it/elettronica/analisi-temporale-di-un-d-pet-flip-flop/</link>
		<comments>https://www.appuntiperscuola.it/elettronica/analisi-temporale-di-un-d-pet-flip-flop/#comments</comments>
		<pubDate>Thu, 03 Feb 2011 09:41:50 +0000</pubDate>
		<dc:creator><![CDATA[admin]]></dc:creator>
				<category><![CDATA[Elettronica]]></category>
		<category><![CDATA[Sistemi digitali]]></category>

		<guid isPermaLink="false">http://localhost:8084/wordpress/?p=1154</guid>
		<description><![CDATA[1)       D-PET Schematic When Preset is  &#8220;1&#8221; and Clear is first &#8220;0&#8221; then &#8220;1&#8221;, the flip-flop starts to store the input values. When Preset is &#8220;1&#8221; and Clear is &#8220;0&#8221; the flip flop&#8217;s output is &#8220;0&#8221;. When Preset and Clear are both &#8220;0&#8221; the outputs gives an indeterminate value, while when they are both &#8220;1&#8221; [&#8230;]]]></description>
		<wfw:commentRss>https://www.appuntiperscuola.it/elettronica/analisi-temporale-di-un-d-pet-flip-flop/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Analisi e sintesi di un sommatore a 2-bit</title>
		<link>https://www.appuntiperscuola.it/elettronica/analisi-e-sintesi-di-un-sommatore-a-2-bit/</link>
		<comments>https://www.appuntiperscuola.it/elettronica/analisi-e-sintesi-di-un-sommatore-a-2-bit/#comments</comments>
		<pubDate>Fri, 21 Jan 2011 18:10:29 +0000</pubDate>
		<dc:creator><![CDATA[admin]]></dc:creator>
				<category><![CDATA[Elettronica]]></category>
		<category><![CDATA[Sistemi digitali]]></category>

		<guid isPermaLink="false">http://localhost:8084/wordpress/?p=1149</guid>
		<description><![CDATA[1) Timing diagram 2) Truth Table (from the simulation) B1 B0 A1 A0 C1 S1 C0 S0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 [&#8230;]]]></description>
		<wfw:commentRss>https://www.appuntiperscuola.it/elettronica/analisi-e-sintesi-di-un-sommatore-a-2-bit/feed/</wfw:commentRss>
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		</item>
		<item>
		<title>Progetto di un convertitore di segno</title>
		<link>https://www.appuntiperscuola.it/elettronica/progetto-di-un-convertitore-di-segno/</link>
		<comments>https://www.appuntiperscuola.it/elettronica/progetto-di-un-convertitore-di-segno/#comments</comments>
		<pubDate>Fri, 21 Jan 2011 18:07:42 +0000</pubDate>
		<dc:creator><![CDATA[admin]]></dc:creator>
				<category><![CDATA[Elettronica]]></category>
		<category><![CDATA[Sistemi digitali]]></category>

		<guid isPermaLink="false">http://localhost:8084/wordpress/?p=1146</guid>
		<description><![CDATA[1) Truth Table In2 In1 In0 Out2 Out1 Out0 Neg 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 1 0 [&#8230;]]]></description>
		<wfw:commentRss>https://www.appuntiperscuola.it/elettronica/progetto-di-un-convertitore-di-segno/feed/</wfw:commentRss>
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		</item>
		<item>
		<title>Analisi funzionale di un network a due livelli combinatori</title>
		<link>https://www.appuntiperscuola.it/elettronica/analisi-funzionale-di-un-network-a-due-livelli-combinatori/</link>
		<comments>https://www.appuntiperscuola.it/elettronica/analisi-funzionale-di-un-network-a-due-livelli-combinatori/#comments</comments>
		<pubDate>Fri, 21 Jan 2011 18:04:00 +0000</pubDate>
		<dc:creator><![CDATA[admin]]></dc:creator>
				<category><![CDATA[Elettronica]]></category>
		<category><![CDATA[Sistemi digitali]]></category>

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		<description><![CDATA[  Timing diagram 2)What is the purpose of this circuit, and the role ofS1, S0 and EN? When the enable switch is “high” the purpose of this circuit is to activate respectively the first, the second, the third and the fourth AND gate through S1 and S0 selectors; while when the enable switch is “ [&#8230;]]]></description>
		<wfw:commentRss>https://www.appuntiperscuola.it/elettronica/analisi-funzionale-di-un-network-a-due-livelli-combinatori/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
	</channel>
</rss>
