Analisi di un 3-bit Shift-Register
1) Schematic
2) Timing diagram
3) Sequence 0 … -4 … -2 … +3 … +1 … 0
Sequence Table:
| !Reset |
Data |
Clock |
Qa | Qb | Qc | Dec |
| 0 | 0 | – | 0 | 0 | 0 | 0 |
| 1 | 0 | ↑ | 0 | 0 | 0 | 0 |
| 1 | 1 | ↑ | 1 | 0 | 0 | -4 |
| 1 | 1 | ↑ | 1 | 1 | 0 | -2 |
| 1 | 0 | ↑ | 0 | 1 | 1 | +3 |
| 1 | 0 | ↑ | 0 | 0 | 1 | +1 |
| 1 | 0 | ↑ | 0 | 0 | 0 | 0 |
Sequence Timing diagram: